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[VHDL-FPGA-Verilog] DE2_NIOS_LITE_SRAM

Description: DE2-SRAM-IP-CORE 需要开发ip core的朋友可以参考哦 ~-DE2-SRAM-IP-CORE need to develop friends can ip core reference Oh ~
Platform: | Size: 1573888 | Author: 张曦 | Hits:

[VHDL-FPGA-Verilog] freerisc8_11

Description: 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
Platform: | Size: 275456 | Author: wfs | Hits:

[VHDL-FPGA-Verilog] BlockRAM

Description: xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
Platform: | Size: 2048 | Author: blackmew | Hits:

[VHDL-FPGA-Verilog] rs1_7seg_pci-0.0.1.tar

Description: Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd. -Raggedstone1 IP core.Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
Platform: | Size: 77824 | Author: 张治国 | Hits:

[VHDL-FPGA-Verilog] AVR_Core

Description: AVR_Core IP CORE .VERY GOOD AS A STUDY FILE-AVR_Core IP CORE. VERY GOOD AS A STUDY FILE
Platform: | Size: 69632 | Author: lijun | Hits:

[VHDL-FPGA-Verilog] can

Description: can IP CORE .VERY GOOD AS A STUDY FILE-can IP CORE. VERY GOOD AS A STUDY FILE
Platform: | Size: 98304 | Author: lijun | Hits:

[VHDL-FPGA-Verilog] Embedded_risc

Description: Embedded_risc IP CORE .VERY GOOD AS A STUDY FILE-Embedded_risc IP CORE. VERY GOOD AS A STUDY FILE
Platform: | Size: 126976 | Author: lijun | Hits:

[VHDL-FPGA-Verilog] I2C_IP_core

Description: I2C IP CORE 及开发文档, 网上搜集-I2C IP CORE and the development of documentation, on-line collection of
Platform: | Size: 452608 | Author: 大熊猫 | Hits:

[VHDL-FPGA-Verilog] vhdl_source

Description: MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
Platform: | Size: 64512 | Author: sq | Hits:

[Software Engineering] SOPCVGAIP3090114

Description: 基于　SOPC　的　VGA　IP　核设计-Based on SOPC the VGA IP core design
Platform: | Size: 460800 | Author: mxl | Hits:

[VHDL-FPGA-Verilog] AVR_Core.tar

Description: vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
Platform: | Size: 59392 | Author: blur | Hits:

[VHDL-FPGA-Verilog] wishbone_VHDL

Description: wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
Platform: | Size: 464896 | Author: 王鹏 | Hits:

[SCM] AVR_Core8F.tar

Description: AVR IP core writen in VHDL. It is beta version, working even with AVR studio
Platform: | Size: 58368 | Author: eldis | Hits:

[Communication-Mobile] bluetooth.tar

Description: 蓝牙的一个ip RTL 核，不知道对大家有没有用？谢谢。-this is an IP core of blutooth.
Platform: | Size: 5120 | Author: 杨力 | Hits:

[VHDL-FPGA-Verilog] usb11

Description: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Platform: | Size: 414720 | Author: 戴求淼 | Hits:

[VHDL-FPGA-Verilog] can

Description: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Platform: | Size: 89088 | Author: 戴求淼 | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[Other Embeded program] cyc2_cmon_080805

Description: Verilog 8051 IP Core for Cyclone -Verilog 8051 IP Core for Cyclone II
Platform: | Size: 63488 | Author: Alx | Hits:

[SCM] 8051IP

Description: Standard 8051 IP Core
Platform: | Size: 49152 | Author: 苗淼 | Hits:

[VHDL-FPGA-Verilog] studyFFTcore

Description: 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
Platform: | Size: 1287168 | Author: 徐成发 | Hits:
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